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如何使用TDR的结果来评估阻抗不连续的影响

E5071C、网络分析仪、TDR、阻抗不连续访问量:18时间:2022-07-18

只有左半部分是相关的。

就像之前提到的,我想检查反射是否是恶化高速信号完整性的原因之一。已经想到的一个方法是通过TDR重新检查PCB线路(在这种情况下,差分微带)、连接器和电缆的阻抗。

从图中可以看出,连接器(1号点附近)的阻抗上下跳动,但当描述PCB线路(1号和2号点之间)时,它又变回正常(约100欧)。

所以我的问题是,现在我已经稍微了解了TDR波的含义,我怎么能知道这个路径是否符合我试图传输的信号?

我是否能从TDR中得到所有的凸起和凹陷,所以我唯一能做的就是根除问题并试图改善它们(比如调整L&C,真的很粗略)?或者我能够把数据放到某种模拟工具中,得到类似电缆-连接器-跟踪路径的传递函数?

这实际上是我们去年设计的一个收发器集成电路,它应该工作在10GHz。显然,我们在端接方面做得不是很好(160欧姆)。我想问的是,我们如何使用TDR的数据?

这些结果是在无电状态下产生的,因为当时我们只是想检查一下线路是否存在阻抗不连续的问题。


TDR技术有几个要素需要考虑。首先是选择TDR仪器的上升时间。理论上,越快越好,但并不总是如此。更快的TDR步骤可以解决阻抗不连续的问题,达到更细的长度,更好地识别设计问题。

但由于EMI和其他原因,每个通信信号都倾向于限制边缘速率。因此,太细的缺陷不会影响实际的信号传播,而TDR仪器中的步长函数的上升时间应与信号边缘的要求一致。因此,比如说,USB2.0的TDR测试规范规定了400ps的边缘,这是通过对数据施加一个滑动滤波器来实现的。对于USB3.0(5Gbps)的TDR边缘被定义为50ps。

由于你的数据速率是10Gbps,我想说仪器需要25ps的边缘速率。您的仪器显示35ps的边缘,这有点低于评估跟踪质量/均匀性所需的速度。

因此,正如你所澄清的,160欧姆的跳跃是由于IC内部的一些可能的纠正性无源电阻造成的,而实际的终端在这一点上是未知的。[通常一个没有电源的集成电路显示其阻抗为无穷大,有一些对地电容]。所以你不能把你的信号完整性可能出现的问题归咎于可怕的160欧姆跳线(还没有)。

连接器周围的不连续现象值得注意。首先,正如我在上面解释的那样,35ps有点低于理想的25ps。因此,如果应用更快的边缘,轨迹将显示更大的偏移。至于有多大,我就不知道了。不连续是L-C型的,L在连接的外面部分(凸起),在那之后有一些寄生电容到地(向下的突波)。对于10Gbps速率来说,阻抗不均匀性并不可怕,但需要注意的是,在电缆-连接器-导线匹配方面需要更好的建模工作。

这也可能是由于你的测试券设计不当造成的突变/下降。

TDR评估最重要的部分是当你给IC通电,并使其完成阻抗自我调整,将端口设置为只接收模式,然后看看从芯片/封装本身真正反射回来的东西。这将是非常重要的。


原文:

How can I use the TDR result to evaluate the effect of impedance discontinuity?

Only the left half is relevant.

Like mentioned before,I want to check out if reflection is one of the reason that deteriorates the signal integrity of high-speed signal.One way that has been come up is to reexamine the impedance of PCB traces(in this case,differential microstrips),connector and cable by TDR.

As can be seen from the pic,the impedance at the connector(around point1) bounces up and down.But then it turns back to normal(about 100ohm)when depicting pcb traces(between point1&2).

So my question is,now that I've been slightly aware of what the TDR wave means,how can I know if this path is eligible for the signal I've tried to transmit?

Are the bumps and dips all I can get from TDR,so that the only thing I can do is to root the problem and try to improve them(like adjust L&C,really roughly)?Or am I able to put the data into some kind of simulation tool and get something like a transfer function for the cable-connector-trace path?

this is actually a transceiver IC we designed last year,and it is supposed to work at 10GHz. Obviously we didn't do a great job in terms of termination(160 Ohms).And what I am gonna ask is,how can we use the data from TDR in general?

These results were produced in unpowered state because then we just wanted to check out if there was a impedance discontinuity problem with the traces.

There are several elements of the TDR technique that should be considered. First one is the selection of rise time of the TDR instrument. Theoretically the faster is better, but not always. Faster TDR step allows to resolve impedance discontinuities to finer length, better identify design problems.

But every communication signal tends to limit the edge rate, for EMI and other reasons. So too fine imperfections do not affect the actual signal propagation, and the rise time of step function in TDR instrument should be aligned with requirements of signal edges. Therefore for, say, the USB 2.0 TDR test specification dictates 400ps edge, which is achieved by imposing a sliding filter on data. For USB3.0 (5Gbps) the TDR edge is defined as 50ps.

Since your data rate is 10Gbps, I would say that the instrument needs the edge rate at 25ps. Your instrument shows 35ps edge, which is a bit below of what is needed to evaluate the trace quality/uniformity.

So, as you clarified, the 160-Ohm jump is due to some likely corrective passive resistor inside the IC, and the actual termination is unknown at this point. [usually an unpowered IC shows its impedance go to infinity, with some capacitance to ground]. So you can't blame the horrible 160-Ohm jump for the possible problems with your signal integrity (yet).

The discontinuity around the connector deserves some attention. First, as I explained above, 35ps is somewhat below the desired 25ps. So the trace would show larger excursions if faster edge will be applied. How much, I can't tell. The discontinuity is of L-C type, with L on outside part of the joint (bump), and some parasitic capacitor to ground (downward glitch) after that. For the 10Gbps rate the impedance inhomogeneity is not really horrible, but it is something that needs an attention and better modeling effort for the cable-connector-trace matching.

It also could be that this blip/dip is due to poor design of your test coupon.

The most important part of TDR evaluation would be when you power-on the IC, and make it to finish impedance self-adjustment, set the port in receive-only mode, and then to see what is really reflected back from the chip/package itself. This will be really important.

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